Complimentary metal oxide semiconductor (CMOS) structures are the core active elements of modern electronics. Undoubtedly, the major material enabling features of Si CMOS are the superb quality of the native silicon dioxide (SiO2), Si/SiO2 interface and high crystalline perfection of the Si substrates. The field effect transistor (FET) implemented as CMOS is scalable. That is, speed and complexity improves with decreasing device feature sizes. This concept makes CMOS architecture a powerful methodology. Deep submicron room-temperature bulk Si CMOS is presently the main technology used for ultra large scale integrated circuits (ULSICs).
Continued scaling of current CMOS architecture is reaching the limits of the material properties of both the SiO2 gate dielectric and bulk Si substrate. Silicon-on-insulator (SOI) substrates offer solutions to both ULSI scaling and high performance wireless architectures. High frequency ULSI requires SOI for reduction in the number of processing steps, reduction of substrate leakage current coupling between FET's, reducing parasitic capacitances and latchup, formation of shallow junctions, isolation of clock noise and functional regions on chip, etc. SOI CMOS offers a 20-35% performance gain over conventional bulk Si CMOS. However, silicon-on-insulator (SOI) substrates are very difficult to produce by most traditional methods.
A solution to the problem of manufacturing silicon-on-insulator (SOI) substrates is disclosed in a copending United States Patent application entitled “Transistor and In-situ Fabrication Process”, filed Mar. 2005, bearing Ser. No. 11/053,785, (applicant's identifying designation Trans A5), and incorporated herein by reference.
Further, many integrated circuits, including ULSICs, include transistors of different types (e.g. switching transistors such as FETs and the like, bipolar transistors, amplifiers) and different conductivities (e.g. n-p-n or p-np). In most instances many additional steps are required to mix various types and conductivities and in some processes it is virtually impossible.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved method of horizontally stacking transistors on a semiconductor substrate.
Another object of the invention is to provide new and improved stacked or integrated transistors and transistor circuits on a common substrate.
Another object of the invention is to provide new and improved method of horizontally stacking transistors of different type and conductivity on a common semiconductor substrate.
Another object of the invention is to provide new and improved method of interconnecting horizontally stacked transistors of different type and conductivity on a common semiconductor substrate.